In the advent of increased demand for consumer electronics and continued growth in semiconductor packing density, more system functionality is integrated onto an integrated circuit. Accordingly, there is an increased need for integration of analog and mixed-mode components (i.e. analog-digital, RF-analog-digital, and mechanical-analog-digital) on the same chip as digital components. Designing such mixed-signal systems-on-chip (SoC) is distinctively challenging since it entails managing system level abstractions while simultaneously dealing with physical effects at the transistor and parasitic levels. In addition, testing next-generation SoCs entails a substantial amount of complexity due to the cost and time-to-market requirements.
An embedded core based SoC IC design conventionally includes various reusable functional blocks, such as microprocessors, interfaces, memory arrays, and digital signal processors (DSPs). These reusable functional blocks are generally referred to as cores. These cores generally include complex analog, mixed signal and digital sub-modules. For example, the SoC may include embedded cores such as an analog-to-digital (ADC) or a digital-to-analog (DAC) converter. In addition, they may include volatile and non-volatile memories.
In general, testing of embedded analog/mixed-signal cores is considered a difficult problem in SoC IC testing. While various design-for-test (DFT) schemes are used to access the embedded analog blocks, the testing is performed by specialized hardware such as mixed-signal automatic test equipment (ATE) or an IC tester. ATEs are widely used by manufacturers of semiconductor components. An ATE executes a test pattern which defines inputs to the device under test (DUT) and the expected outputs. By executing the test pattern, the ATE determines whether the component is operating properly.
Texas Instruments™ Inc.'s Asymmetric Digital Subscriber Line (ADSL) client premise equipment (CPE) modem, Sangam™ (i.e.TNETD7300), has an ADSL line driver module, power management module and a variety of digital modules including memory, processor, and host interfaces. Testing such a device is a challenge regarding coverage as well as expense; where coverage implies the amount of silicon which must be tested before it is shipped to customers. For digital modules, coverage can be quantitatively derived from the scan test coverage. For analog modules, coverage is qualitative and is based on the amount of testing (functional/parametric) performed on each analog block. For SoC devices, the coverage for analog blocks may reduce in the absence of test modes to fully access these blocks. Test cost directly stems from the amount of time to perform all testing. Using an ATE each second of test time costs approximately three cents. Thus, for sequential testing of analog and digital modules incorporated within the SoCs using an ATE, the test time and expense may be double in a worst case scenario.
The methodology for testing digital and analog blocks differs substantially. Digital blocks are tested for modeled defects largely using algorithmically generated test patterns, (e.g. automatic test pattern generator (ATPG) or memory built-in-self-test (memory BIST)). On the other hand, analog blocks are tested for functionality and characterized for specific parameters. The digital test set typically comprises of scan patterns for different fault models that are applied under burn-in and voltage box (VBox) conditions where VBox is a condition which stresses the digital logic by changing the power supply rail voltage VDD to bring out latent defects of the digital blocks. For example, if the nominal operational voltage is 1.5V, VBox limits may be 1.1V and 2.1V. In such a case, a device may be stressed using a VDD of 2.1V volts and then tested at 1.1V to bring out a defect, which depends upon the process and the statistical data. Moreover, the digital test set includes memory tests typically in the form of memory BIST. These aforementioned digital test sets differ from I/O characterization and at-speed tests. During these tests, the device is configured into scan test mode where device functionality is lost. In contrast, during analog testing (i.e. signal-to-noise ratio (SNR) and total harmonic distortion (THD)), the tests are required to be performed only when the device is in a functional operating mode. This requirement imposes the restriction that each analog and digital block be separately and sequentially tested to avoid any conflict of the scan and functional testing.
Accordingly, SoCs have been tested in the past by testing the analog and digital blocks of the chip separately and/or sequentially by enabling a power down feature for each individual block. In addition, the inputs and outputs of all blocks are multiplexed to external pins for access. The disadvantage of this approach is that a large amount of test time is required to test the entire SoC device since it is difficult to test various blocks having different test methodologies in parallel.
The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above.